This application claims priority from Korean Patent Application No. 2000-80426, filed Dec. 22, 2000, the contents of which are hereby incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to cross-coupled transistor pairs and methods of constructing cross-coupled transistor pairs.
2. Description of Related Art
In conventional cross-coupled transistor pair layouts, significant differences may exist between the length of a line connecting a gate of a first transistor to a node of the second transistor and the length of a line connecting a gate of the second transistor to a node of the first transistor. As a result, a gate loading and a junction loading of the two transistors forming the cross-coupled transistor pair may differ from each other. When differences occur between the gate loading and the junction loading of the transistors, the cross-coupled transistor pair may not operate as desired.
FIG. 1 is a circuit diagram illustrating a conventional cross-coupled transistor pair configuration. The cross-coupled transistor pair includes a first PMOS transistor PM1 and a second PMOS transistor PM2. The first PMOS transistor PM1 includes a source that receives a power supply voltage VCC, a drain connected to a node xe2x80x9caxe2x80x9d, and a gate connected to a node xe2x80x9cbxe2x80x9d. The second PMOS transistor PM2 includes a source that receives the power supply voltage VCC, a drain connected to the node xe2x80x9cbxe2x80x9d, and a gate connected to the node xe2x80x9caxe2x80x9d.
Operation of the cross-coupled transistor pair of FIG. 1 is as follows. If a voltage of the node xe2x80x9caxe2x80x9d has a logic xe2x80x9chighxe2x80x9d level and a voltage of the node xe2x80x9cbxe2x80x9d has a logic xe2x80x9clowxe2x80x9d level, the first PMOS transistor PM1 is turned on and the power supply voltage VCC is applied to the node xe2x80x9caxe2x80x9d. The second transistor PM2 is thereby turned off. Alternatively, if a voltage of the node xe2x80x9caxe2x80x9d has a logic xe2x80x9clowxe2x80x9d level and a voltage of the node xe2x80x9cbxe2x80x9d has a logic xe2x80x9chighxe2x80x9d level, the second PMOS transistor PM2 is turned on and the power supply voltage VCC is applied to the node xe2x80x9cbxe2x80x9d. The first PMOS transistor PM1 is thereby turned off. The cross-coupled transistor pair of FIG. 1 therefore acts as a latch to latch levels of the nodes xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d.
FIGS. 2A to 2D are plan views schematically illustrating a conventional method of constructing the cross-coupled transistor pair of FIG. 1. Referring to FIG. 2A, separate first and second active areas PM1A, PM2A, corresponding to the first and second PMOS transistors PM1, PM2, respectively, are arranged on a substrate (not shown).
As shown in FIG. 2B, a first gate area PM1G is then arranged longitudinally on a portion of the first active area PM1A between a first source area PM1S and a first drain area PM1D. A second gate area PM2G is longitudinally arranged on a portion of the second active area PM2A between a second source area PM2S and a second drain area PM2D. A terminal of the first gate area PM1G extends perpendicularly to the right of the first active area PM1A to connect to the second drain area PM2D. A terminal of the second gate area PM2G extends perpendicularly to the left of the second active area PM2A to connect to first the drain area PM1D. The first and second gate areas PM1G, PM2G are indicated by cross-hatching.
Subsequently, as shown in FIG. 2C, first and second metal lines PM1M1, PM2M1 are arranged longitudinally on the first and second source areas PM1S, PM2S, respectively, to receive the power supply voltage VCC. Third and fourth metal lines PM1M2, PM2M2 are longitudinally arranged on the first and second drain areas PM1D, PM2D to connect to the second and first gate areas PM2G, PM1G, respectively. The first and second gate areas PM1G, PM2G correspond to the first and second PMOS transistors PM1, PM2, respectively. The first through fourth metal lines PM1M1, PM2M1, PM1M2, PM2M2 are indicated by reverse cross-hatching.
Referring to FIG. 2D, contacts CON1 connect the first and second metal lines PM1M1, PM2M1 to the first and second source areas PM1S, PM2S. Contacts CON1 also connect the third and fourth metal lines PM1M2, PM2M2 to the first and second drain areas PM1D, PM2D, and connect the first and second gate areas PM1G, PM2G to the fourth and third metal lines PM2M2, PM1M2, respectively. Unfortunately, the distance from the node xe2x80x9caxe2x80x9d to a position xe2x80x9ccxe2x80x9d on the second gate area PM2G is different than the distance from the node xe2x80x9cbxe2x80x9d to a position xe2x80x9cdxe2x80x9d on the first gate area PM1G. As a result, the cross-coupled transistor pair may not operate as designed.
FIG. 3 is a circuit diagram schematically illustrating another conventional cross-coupled transistor pair configuration. Referring to FIG. 3, a cross-coupled transistor pair according to this configuration includes first and second PMOS transistors PM3, PM4. The first PMOS transistor PM3 has a source connected to a data input/output (I/O) line DIO, a gate connected to a node xe2x80x9cfxe2x80x9d, and a drain connected to a node xe2x80x9cexe2x80x9d. The second PMOS transistor PM4 includes a source connected to an inverted data I/O line DIOB, a gate connected to the node xe2x80x9cexe2x80x9d, and a drain connected to the node xe2x80x9cfxe2x80x9d. This cross-coupled transistor pair arrangement provides a current sense amplifier for a data I/O line pair DIO, DIOB of a semiconductor memory device.
FIGS. 4A to 4E are plan views schematically illustrating a method of constructing the cross-coupled transistor pair of FIG. 3, according to the prior art. Referring first to FIG. 4A, first and second active areas PM3A, PM4A, corresponding to the first and second transistors PM3, PM4, respectively, are separately arranged on a substrate (not shown). Referring to FIG. 4B, a first gate area PM3G is longitudinally arranged on a portion of the first active area PM3A between a first source area PM3S and a first drain area PM3D. A second gate area PM4G is longitudinally arranged on a portion of the second active area PM4A between a second source area PM4S and a second drain area PM4D. A terminal of the first gate area PM3G extends perpendicularly to the left of the first active area PM3A to connect to the second drain area PM4D. A terminal of the second gate area PM4G extends perpendicularly to the right of the second active area PM4A to connect to the first drain area PM3D. The first and second gate areas PM3G, PM4G are indicated using cross-hatching.
As shown in FIG. 4C, a first signal line BP1 is arranged outside the active areas in a transverse direction to provide a connection between the first drain area PM3D, corresponding to the first PMOS transistor PM3, and the second gate area PM4G, corresponding to the second PMOS transistor PM4. A second signal line BP2 is also arranged transversely outside the active areas to provide a connection between the second drain area PM4D, corresponding to the second PMOS transistor PM4, and the first gate area PM3G, corresponding to the first PMOS transistor PM3.
Next, as shown in FIG. 4D, first and second metal lines PM3M1, PM4M1, corresponding to the data I/O line pair DIO, DIOB (see FIG. 3), are arranged longitudinally on the first and second source areas PM3S, PM4S, respectively. Third and fourth metal lines PM3M2, PM4M2 are arranged longitudinally on respective ones of the first and second drain areas PM3D, PM4D to connect them to the first and second signal lines BP1, BP2, respectively. Fifth and sixth metal lines M1, M2 are arranged outside the first and second active areas PM3A, PM4A to connect the first and second signal lines BP1, BP2 to the second and first gate areas PM4G, PM3G, respectively.
Finally, as shown in FIG. 4E, contacts CON2 are arranged to connect the first and second metal lines PM3M1, PM4M1 to the first and second source areas PM3S, PM4S, respectively. Contacts CON2 further connect the third and fourth metal lines PM3M2, PM4M2 to the first and second drain areas PM3D, PM4D, respectively; the third and fourth metal lines PM3M2, PM4M2 to the first and second signal lines BP1, BP2, respectively; the fifth and sixth metal lines M1, M2 to the first and second gate areas PM3G, PM4G, respectively; and the fifth and sixth metal lines M1, M2 to the second and first signal lines BP2, BP1, respectively.
In the cross-coupled transistor pair layout of FIGS. 4A to 4E, a line length from node xe2x80x9cexe2x80x9d to a terminal xe2x80x9cgxe2x80x9d on the gate area PM4G of the second PMOS transistor PM4 is equal to that of a line length from node xe2x80x9cfxe2x80x9d to a terminal xe2x80x9chxe2x80x9d on the gate area PM3G of the first PMOS transistor PM3. Accordingly, there is no difference between the gate loading and the junction loading of the first PMOS transistor PM3 and the second PMOS transistor PM4, and the cross-coupled transistor pair operates as designed.
Unfortunately, however, since the fifth and sixth metal lines M1, M2 are arranged outside the first and second active areas PM3A, PM4A, the cross-coupled transistor pair layout of FIGS. 4A to 4E has an increased layout size. An increase in layout size leads to an increase in a total size of a semiconductor memory device.
FIG. 5 is a circuit diagram illustrating yet another conventional cross-coupled transistor pair configuration. The cross-coupled transistor pair of FIG. 5 includes first and second NMOS transistors NM1, NM2. The first NMOS transistor NM1 includes a drain connected to a bit line BL, a gate connected to a node xe2x80x9cjxe2x80x9d, and a source to which a control signal LAB is applied. The second NMOS transistor NM2 includes a drain connected to an inverted bit line BLB, a gate connected to a node xe2x80x9cixe2x80x9d, and a source to which the control signal LAB is applied. The cross-coupled transistor pair of FIG. 5 can be used as an NMOS bit line sense amplifier, connected between a bit line pair BL, BLB of a semiconductor memory device.
FIGS. 6A to 6E are plan views schematically illustrating a conventional layout method for constructing the cross-coupled transistor pair of FIG. 5. First, referring to FIG. 6A, an active area NMA is arranged on a substrate (not shown). Referring next to FIG. 6B, a first gate area NM1G is arranged on an upper portion of the active area NMA between a first drain area NM1D and a common source area NMS. A second gate area NM2G is arranged on a lower portion of the active area NMA between a second drain area NM2D and the common source area NMS.
The first drain area NM1D corresponds to the first NMOS transistor NM1 and is separated from the common source area NMS by the first gate area NM1G. The first gate area NM1G has an approximately letter xe2x80x9cUxe2x80x9d shape of a predetermined thickness. The second drain area NM2D corresponds to the second NMOS transistor NM2 and is separated from the common source area NMS by a second gate area NM2G. The second gate area NM2G has an inverted letter xe2x80x9cUxe2x80x9d shape of a predetermined thickness.
Referring to FIG. 6C, first and second signal lines BP3, BP4 are arranged longitudinally on the common source area NMS on a left side of the first gate area NM1G and a right side of a second gate area NM2G, respectively. The first and second signal lines BP3, BP4 transmit data from the bit line pair BL, BLB. The first signal line BP3 connects the first drain area NM1D, corresponding to the first NMOS transistor NM1, with the second gate area NM2G, corresponding to the second NMOS transistor NM2. The second signal line BP4 connects the first gate area NM1G, corresponding to the first NMOS transistor NM1, with the second drain area NM2D, corresponding to the second NMOS transistor NM2.
Referring now to FIG. 6D, a first metal line M3 is arranged transversely on a portion of the common source area NMS between the first and second gate areas NM1G, NM2G to transmit a control signal LAB. Finally, as shown in FIG. 6E, contacts CON3 are arranged to connect the first signal line BP3 to the first drain area NM1D and the second gate area NM2G. Contacts CON3 also connect the second signal line BP4 to the first gate area NM1G and the second drain area NM2D. A contact also connects the metal line M3 to the common source area NMS.
In the conventional cross-coupled transistor pair layout shown in FIGS. 6A to 6E, a difference occurs between the distance from the node xe2x80x9cixe2x80x9d to the second gate area NM2G and the distance from the node xe2x80x9cjxe2x80x9d to the first gate area NM1G. Since these different distances may cause the first and second NMOS transistors NM1, NM2 to experience a difference between the gate loading and the junction loading thereof, this conventional cross-coupled transistor pair layout may not operate as designed.
As described above, conventional layout methods for cross-coupled transistor pairs may not operate as designed because of differences between gate loading and junction loading of the transistors. Furthermore, in the conventional cross-coupled transistor pair layout methods, a threshold voltage of the two transistors depends on a density of impurities implanted into the gate area. However, since the two transistors are generally spaced apart from and parallel to each other, a density of the impurities implanted into the gate areas varies from one gate area to the other. Using the conventional layout method, a threshold voltage difference may therefore occur between the two transistors that constitute the cross-coupled transistor pair, and the cross-coupled transistor pair will not operate as designed.
Various embodiments of the present invention provide cross-coupled transistor pair layouts that perform a stable and reliable operation.
According to a preferred embodiment of the present invention a cross-coupled transistor pair includes separately arranged first and second active areas. A gate area of a first transistor is arranged symmetrically on portions of the first and second active areas. A gate area of a second transistor is also arranged symmetrically on portions of the first and second active areas. A first signal line extends between drain areas of the first transistor and the gate area of the second transistor. A second signal line extends between drain areas of the second transistor and the gate area of the first transistor. Metal lines can be provided to connect a source voltage, data signal lines, or control signals to common source areas of the first and second transistors. Methods for constructing cross-coupled transistor pairs are also provided.